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nx2601 1 rev. 2.3 12/01/06 typical application description the nx2601 controller ic is a triple controller with a dual channel synchronous buck controller ic and an ldo con- troller designed for multiple converters such as pcie graphic card applications .the two synchronous pwm controllers are 180 degree out of phase which reduces the input ripple current, allowing to reduce the # of input capacitors.another main feature of the part is that it can operate from single 12v supply while maintaining a regu- lated 5v supply for the biasing and the internal drivers. other features of nx2601 are: programmable frequency from 200khz to 1mhz, independent digital soft start and enable pins for each controller which allows for different power sequencing, adaptive driver provides optimized ef- ficiency while maintain sufficient deadband, vcc undervoltage lock out and current limiting using an rds- on of the external mosfet with hiccup feature. n two channel pwm with out of phase operation n individual digital soft start for two pwm output and ldo controller n bus voltage operation from 2v to 25v n hiccup current limit by sensing rdson of mosfet n adjustable frequency up to 1mhz per channel n adaptive deadband time n three enable pin available allows for independent power sequencing n mlpq-32l package offers small size n pb-free and rohs compliant ordering information features dual synchronous pwm controller with nmos ldo controller & 5v bias regulator applications preliminary data sheet evaluation board available. device temperature package frequency pb-free NX2601CMTR 0 to 70 o c mlpq-32l 200khz to 1mhz yes figure1 - typical application of 2601 vin1 6.8k r20 r21 1.25k 0 4 5 150pf c18 150uf c19 150uf c20 2n3904 47pf c16 68uf c17 31 30 6 2 1 3 7 8 9 10 11 n x 2 6 0 1 +2.5v/2a vout3 +3.3v vin2 +5v r24 62k c21 1nf r18 1.5k 1.25k r19 r16 5k 2.35k r17 r15 m5 1uf c15 10 r12 5k gnd vref vp rt ensw2 ensw1 enldo ldo fb ldo out reg out reg fb vcc 10.5k r1 1uf c1 c5 8.2nf c3 c2 d1 r4 20.8k c6 r2 2.7nf 28 29 27 +12v vin1 +5v +1.2v@15a vout1 r3 10.4k 100uf 180uf r5 5k l1 1uh 21 23 0.1uf c4 24 2 x (2r5tpd680m6,680uf,6mohm) c7 l2 0.78uh m2 m1 25 26 22 pvcc1 ocp1 pgnd1 bst1 fb1 comp1 sw1 hdrv1 ldrv1 1.5k 6k r6 1uf c8 c12 10nf c9 d2 r9 6.97k c13 r7 3.3nf 13 12 14 +1.8v/10a vout2 r8 8.7k 180uf r10 5k 20 18 0.1uf c11 17 3 x (4tpe150m,150uf,18mohm) c14 l4 1.5uh m4 m3 16 15 19 pvcc2 ocp2 pgnd2 bst2 fb2 comp2 sw2 hdrv2 ldrv2 820 auxvcc 1.65k r13 r11 +5v c22 220pf c23 220pf vin1 1uf c24 1uf c25 off on 2n3904 10k r27 r28 10k off on 2n3904 10k r25 r26 10k 5k patent pending n pci graphic card on board converters n vddq supply in mother board applications n on board dc to dc such as 12v to 3.3v, 2.5v or 1.8v n fpga and set top box applications pb free product
nx2601 2 rev. 2.3 12/01/06 absolute maximum ratings vcc,pvcc & bst to sw voltage ......................... 6.5v bst voltage ...................................................... 35v sw ................................................................... -5v(note1) to 35v auxvcc .......................................................... 35v all other pins .................................................... gnd to vcc+0.3v storage temperature range ............................... -65 o c to 150 o c operating junction temperature range ............... -40 o c to 125 o c caution: stresses above those listed in "absolute maximum ratings", may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. package information 32-lead 5x5 plastic mlpq o ja c/w q?35 nx2601 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 17 25 26 27 28 29 30 31 32 fb2 comp2 gnd vcc ensw1 ensw2 enldo rt ldo fb ldo out comp1 fb1 hdrv1 sw1 ocp1 vp vref nc auxvcc reg out reg fb ocp2 sw2 hdrv2 pgnd1 pgnd2 bst1 pvcc1 ldrv1 ldrv2 pvcc2 bst2 electrical specifications unless otherwise specified, these specifications apply over vcc = 5v, v bst -v sw =5v, ensw1=high, ensw2=high, enldo=high, and t a = 0 to 70 o c . typical values refer to t a = 25 o c . low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. parameter sym test condition min typ max units reference voltage fb voltage fb voltage line regulation vcc supply voltage vcc voltage range vcc static supply current vcc dynamic supply current v bst voltage range v bst static supply current v bst dynamic supply current 4.5 < vcc < 5.5 outputs not switching freq=600khz, c load = 3300pf outputs not switching freq = 600khz, c load = 3300pf 4.5 4.5 0.800 0.4 5.0 2.0 8 5.0 2.0 tbd 5.5 5.5 v % v ma ma v ma ma v ref v cc i cc_sta i cc_dyn v bst i bst_sta i bst_dyn 4.
nx2601 3 rev. 2.3 12/01/06 parameter sym test condition min typ max units under voltage lockout uvlo threshold - vcc v cc_uvlo uvlo hysteresis - vcc v cc__hyst uvlo threshold - v auxvcc v aux_uvlo uvlo hysteresis - v auxvcc v aux_hyst error amplifiers open loop gain input bias current input offset voltage oscillator frequency f s ramp amplitude v ramp en & ss soft start time t ss enable threshold voltage enable hysterises ldo controller ldo fb voltage fb pin bias current ldo_out output voltage high ldo_out output voltage low open loop gain 5v aux reg reg fb voltage fb pin bias current reg_out output voltage high reg_out output voltage low open loop gain high side driver (cl=3300pf) output impedance, sourcing r source _ h current output impedance , sinking r sink _ h current rise time t hdrv_rise fall time t hdrv_fall deadband time t dead_lh supply ramping up supply ramping down supply ramping up supply ramping down rt=30k,measured at the output drive fs=600khz enable ramp up ldoout=ldofb auxvcc=24v,ldo fb=0.7v i o_source =1.4ma auxvcc=24v,ldo fb=0.9v i o_sink =1.4ma gbnt(note2) -0.2 22 50 -0.2 22 50 4 0.2 7 0.7 65 0.3 0 600 1 3.41 1.25 100 0.8 0 23.5 0.2 1.25 0 23.5 0.2 0.85 0.65 25 20 30 v v v v db ua mv khz v ms v mv v m a v v db v m a v v db ohm ohm ns ns ns regout=regfb auxvcc=24v,reg fb=1.1v i o_source =1.4ma auxvcc=24v,reg fb=1.4v i o_sink =1.4ma gbnt(note2) 10% to 90% 90% to 10% ldrv going low to hdrv going high, 10% to 10%
nx2601 4 rev. 2.3 12/01/06 parameter sym test condition min typ max units 0.85 0.5 25 20 20 ohm ohm ns ns ns low side driver (cl=3300pf) output impedance, sourcing r source _ l current output impedance , sinking r sink _ l current rise time t ldrv_rise fall time t ldrv_fall deadband time t dead_hl 10% to 90% 90% to 10% sw going low to ldrv going high, 10% to 10% note 2: this parameter is guaranteed by design but not tested in production(gbnt). note 1: 500ns transient. this pin can withstand -2v dc.
nx2601 5 rev. 2.3 12/01/06 pin descriptions pin # pin symbol pin description a resistor divider is connected from the respective switcher bus voltages to these pins that holds off the controllers soft start until this threshold is reached. an external low cost mosfet or npn transisitor can be connected to this pin for external enable control. a resistor divider is connected from the ldo bus voltage to this pin that holds off the ldo soft start until this threshold is reached. an external low cost mosfet can be connected to this pin for external enable control. analog ground. ic's supply voltage. this pin biases the internal logic circuits. a high freq 1uf ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. oscillator's frequency can be set by using an external resistor from this pin to gnd. this frequency is the master clock frequency which is internally divided by two to set each controller frequency. ldo controller feedback input. if the ldofb pin is pulled below 0.5*vref, an internal comparator after certain delay and pulls down ldoout pin and initiates the hiccup circuitry. during the startup this latch is not activated, allowing the ldofb pin to come up and follow the soft started vref voltage. ldo controller output. this pin is controlling the gate of an external nch mosfet. the maximum rating of this pin is 16v. this pin is the supply voltage for the ldo controller as well as the 5v regulator controller that regulates the voltage at vcc derived from the bus voltage. the maximum voltage applied to this pin is 30v. the output of the 5v regulator controller that drives a low current low cost external bipolar transistor or an external mosfet to regulate the voltage at vcc pin derived from bus voltage. this eliminates an otherwise external regulator needed in applications where 5v is not available. feedback pin of the 5v regulator controller. a resistor divider is connected from the output of the 5v regulator to this pin to complete the loop. this pin is the error amplifiers inverting input. these pins are connected via resistor dividers to the output of the switching regulators to set the output dc voltage. these pins are the outputs of error amplifiers and are used to compensate the respective voltage control feedback loops. 1 2 3 4 5 6 7 8 9 10 11 12 29 13 28 ensw1 ensw2 enldo gnd vcc rt ldo fb ldo out auxvcc regout regfb fb2 fb1 comp2 comp1 rer
nx2601 6 rev. 2.3 12/01/06 pin descriptions pin # pin symbol pin description this pin is connected to the drain of the external low side mosfet and is the input of the over current protection(ocp) comparator. an internal current source which equals 1.25v divided by rt resistor is flown to the external resistor which sets the ocp voltage across the rdson of the low side mosfet. current limit point is this voltage divided by the rds-on. once this threshold is reached the hdrv and ldrv pins are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048 switching cycles. these pins are connected to source of high side fets and provide return path for the high side drivers. they are also used to hold the low side drivers low until this pin is brought low by the action of high side turning off. ldrvs can only go high if sw is below 1v threshold . high side gate driver outputs. this pin supplies voltage to high side fet driver. a high freq 1uf ceramic capaci- tor is placed as close as possible to and connected to these pins and respected sw pins. supply voltage for the low side fet drivers. a high frequency 1uf ceramic cap must be connected from this pin to the pgnd1 and pgnd2 pin as close as possible to the pins. low side gate driver outputs. power ground pin for low side drivers. this pin is the first error amplifier non-inverting input. this pin should be con- nected either to an external reference voltage (tracking application) or to the internal reference voltage provided by this device. reference voltage available. a 100pf capacitor can be connected from this pin to gnd. this pin is held low until internal vcc uvlo and the ensw1 pin are good, allowing it to soft start. 14 27 15 26 16 25 17 24 18 23 19 22 20 21 30 31 32 ocp2 ocp1 sw2 sw1 hdrv2 hdrv1 bst2 bst1 pvcc2 pvcc1 ldrv2 ldrv1 pgnd2 pgnd1 vp vref nc
nx2601 7 rev. 2.3 12/01/06 block diagram bias generator 1.25v 0.8v vcc bst1 drvh1 sw1 pvcc1 drvl1 fb1 comp1 two phase osc r s q digital start up uvlo por_ldo 1.25/1.15 ensw1 gnd control logic ocp comparator pgnd1 ocp1 por_sw bias auxvcc regfb regout 9.6/9.2 4/3.8 set1 ramp1 channel 1 pwm controller channel 2 pwm controller (exclude oscillator) fb2 comp2 ensw2 bst2 drvh2 sw2 pvcc2 drvl2 pgnd2 ocp2 enldo 1.25/1.15 digital start up ldoout fbldo ldo control logic por_ldo rt vref vp 0.4 uvlo por_sw
nx2601 8 rev. 2.3 12/01/06 1uf r26 0 4 5 150pf c3 150uf c4 150uf c5 q2 47pf c7 68uf c17 31 30 6 2 1 3 7 8 9 10 11 n x 2 6 0 1 +2.5v/2a vout3 +3.3v vin3 +5v r2 62k c1 100pf r9 2.7k 1.25k r3 r8 6.8k 1.25k r4 r7 1.5k 1.25k r5 r11 5k 2.35k r6 r10 m5 1uf c10 10 r16 5k gnd vref vp rt ensw2 ensw1 enldo ldo fb ldo out reg out reg fb vcc 10.5k r22 1uf c41 c17 8.2nf d1 r25 20.8k c19 2.7nf 28 29 27 +12v vin1 +5v +1.2v@15a vout1 r27 10.4k 39uf 180uf r24 5k l2 1uh 21 23 0.1uf c11 24 680uf,6mohm c13,c14 l1 0.78uh q5 q4 25 26 22 pvcc1 ocp1 pgnd1 bst1 fb1 comp1 sw1 hdrv1 ldrv1 1.5k 3k r32 1uf c42 c37 10nf d2 r35 2.7k c25 r28 8.2nf 13 12 14 +1.8v@10a vout2 r29 3.5k r33 5k 20 18 0.1uf c31 17 150uf,18mohm c26,27,28 l3 1.5uh q7 q6 16 15 19 pvcc2 ocp2 pgnd2 bst2 fb2 comp2 sw2 hdrv2 ldrv2 330 auxvcc 1.65k r15 r19 +5v c18 220pf c32 220pf vin1 vin1 c21 c23 c24 r23 c12 470pf 20k 1uf +5v vin2 39uf 180uf l4 1uh c33 c36 c38 r34 c34 20k 470pf 33uf c8 5k r13 vin2 c2 100pf r1 1k simplified demo board schematic
nx2601 9 rev. 2.3 12/01/06 figure 2 - demo board schematic based on orcad d2 d1n5819 pvcc vcc 5 pvcc2 18 pvcc1 23 bst1 24 hdrv1 25 ocp1 27 ldrv1 22 sw1 26 fb1 29 comp1 28 bst2 17 hdrv2 16 sw2 15 ocp2 14 ldrv2 19 fb2 12 comp2 13 pgnd1 21 pgnd2 20 agnd 4 vref 31 vp 30 rt 6 en_sw2 2 en_sw1 1 en_ldo 3 ldo_fb 7 ldo_out 8 aux_vcc 9 reg_out 10 reg_fb 11 nc 32 u1 nx2601_mlpq tp7 2 3 4 5 1 j5 c40 .1u pvcc c10 1u c41 1u pvcc pvcc c1 100p size document number rev date: sheet of 1 1 thursday, march 24, 2005 a nx2601-02 evl brd schematic sw2_in 2 3 4 5 1 j7 r1 1k 1 2 3 4 5 6 7 8 q7 irf7822 r2 62k r3 1.25k r4 1.25k r5 1.25k l1 do5010p-781hc r6 2.35k sw2_in r7 1.5k r8 6.8k r9 2.7k 1 2 j2 r26 1.5k ldo_in ldo_in r27 10.4k ldo_in l3 do5010p-222hc 1 2 j3 sw1_in sw2_out r28 330 r29 3.5k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j8 c42 1u c25 8.2nf r18 0 sw2_in c26 4tpe150m c27 4tpe150m c19 2.7n c28 4tpe150m c29 op r19 10 c31 .1u r30 0 ldo_in r17 0 r31 0 r32 3k l4 do1603c-102 sw2_in sw2 r10 0 c3 150pf c33 16svpa39maa r33 4.99k tp5 r34 20k c34 470p c35 op c36 16svpa180m c37 10n c38 1u r35 2.7k r11 4.99k r12 0 sw1_in r36 1k sw1_in c8 16tqc33m c13 2r5tpd680m6 1 2 j9 c14 2r5tpd680m6 tp3 q1 mtd3055e c4 4tpe150m c9 6tpb68m c15 op c16 op ldo_in sw1_out vcc2 c5 4tpe150m tp1 1 2 3 4 5 6 7 8 q6 irf7822 ldo_out tp2 ldo_out c11 .1u 2 3 4 5 1 j1 c20 op c6 .1u r20 0 r21 0 r22 10.5k l2 do1603c-102 q4 irf3706 q5 irf3706 q2 2n3904 sw1_in q3 op sw1 c2 100p r13 4.99k sw1 c17 220p package: mlpq32l sw2 c21 16svpa39maa r14 0 r24 4.99k c7 47p tp4 2 3 4 5 1 j4 sw2_in r23 20k c12 470p c22 op r15 1.65k c23 16svpa180m c18 8.2n c24 1u c39 .1u vcc1 tp6 r25 20.8k sw2_in r16 4.99k 2 3 4 5 1 j6 d1 d1n5819 c32 220p pvcc c30 op
nx2601 10 rev. 2.3 12/01/06 bill of materials item number quantity value manufacture 1 2 c2,c1 100p 2 1 c3 150pf 3 5 c4,c5,c26,c27,c28 4tpe150m sanyo 4 5 c6,c11,c31,c39,c40 .1u 5 1 c7 47p 6 1 c8 16tqc33m sanyo 7 1 c9 6tpb68m sanyo 8 5 c10,c24,c38,c41,c42 1u 9 2 c12,c34 470p 10 2 c14,c13 2r5tpd680m6 sanyo 11 9 q3,r14,c15,c16,c20,c22, op c29,c30,c35 12 2 c17,c32 220p 13 1 c18 8.2n 14 1 c19 2.7n 15 2 c21,c33 16svpa39maa sanyo 16 2 c36,c23 16svpa180m sanyo 17 1 c25 8.2nf 18 1 c37 10n 19 2 d1,d2 d1n5819 20 5 j1,j4,j5,j6,j7 scope tp tektronics 21 3 j2,j3,j9 con2 22 1 j8 con20b 23 1 l1 do5010p-781hc coilcraft 24 2 l2,l4 do1603c-102 25 1 l3 do5010p-222hc 26 1 q1 mtd3055e 27 1 q2 2n3904 28 2 q4,q5 irf3706 international rectifier 29 2 q7,q6 irf7822 international rectifier 30 1 r1 1k 31 1 r2 62k 32 3 r3,r4,r5 1.25k 33 1 r6 2.35k 34 2 r7,r26 1.5k 35 1 r8 6.8k 36 2 r35,r9 2.7k 37 8 r10,r12,r17,r18,r20,r21, 0 r30,r31 38 5 r11,r13,r16,r24,r33 4.99k 39 1 r15 1.65k 40 1 r19 10 41 1 r22 10.5k 42 2 r34,r23 20k 43 1 r25 20.8k 44 1 r27 10.4k 45 1 r28 330 46 1 r29 3.5k 47 1 r32 3k 48 1 r36 10k 49 7 tp1,tp2,tp3,tp4,tp5,tp6, tp tp7 50 1 u1 nx2601_mlpq nexsem inc.
nx2601 11 rev. 2.3 12/01/06 demoboard waveforms figure 3 - start up waveform of vcc by internal regulator. ch1(auxvcc), ch3( vcc&pvcc) figure 7-transient response for first channel 1.2v output figure 4 - soft start for channel 1 1.2v and chanel 2 1.8v output figure 5 - soft start for channel 1 1.2v and ldo output figure 6 - output ripple for power output ch1 and ch2 figure 8 -transient reponse for channel 1. (zoomed)
nx2601 12 rev. 2.3 12/01/06 figure 9 - ch2 1.8v output transient 0 to 9a. figure 10 - ch2 1.8v transient (zoomed) figure 11 - transient response for 2.5v ldo output demo board waveforms (cont') figure 14 - ldo in short. all channels go into hiccup. figure 13 - ch2 is in short. all channels are in hiccup. figure 12 - ch1 is short. all channels go into hiccup.
nx2601 13 rev. 2.3 12/01/06 application information symbol used in application information: v in - input voltage v out - output voltage i out - output current d v ripple - output voltage ripple f s - switching frequency d i ripple - inductor current ripple design example power stage design requirements: v in =12v v out =1.2v i out =15a d v ripple <=20mv d v tran <=100mv @ 15a step f s =300khz output inductor selection the selection of inductor value is based on induc- tor ripple current, power rating, working frequency and efficiency. larger inductor value normally means smaller ripple current. however if the inductance is chosen too large, it brings slow response and higher cost. usually the ripple current ranges from 20% to 40% of the output current. this is a design freedom which can be decided by design engineer according to various application re- quirements. the inductor value can be calculated by using the following equations: inout out out rippleins rippleoutput v-vv 1 l= ivf i=ki d ...(1) where k is between 0.2 to 0.4. select k=0.3, then out out 12v-1.2v1.2v1 l= 0.315a12v300khz l=0.8uh choose l out =0.78uh, then coilcraft inductor do5010p-781hc is a good choice. current ripple is calculated as inout out ripple outins v-vv 1 i= lvf 12v-1.2v1.2v1 =4.6a 0.78uh12v300khz d = ...(2) output capacitor selection output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(dc) load condition as well as specification for the load transient. the optimum design may require a couple of iterations to satisfy both condition. based on dc load condition the amount of voltage ripple during the dc load condition is determined by equation(3). d d=d+ ripple rippleripple sout i vesri 8fc ...(3) where esr is the output capacitors' equivalent series resistance,c out is the value of output capacitors. typically when large value capacitors are selected such as aluminum electrolytic,poscap and oscon types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. for this example, poscap are chosen as output capacitors, the esr and inductor current typically de- termines the output voltage ripple. d ==w d ripple desire ripple v 20mv esr=4.3m i4.6a ...(4) if low esr is required, for most applications, mul- tiple capacitors in parallel are better than a big capaci- tor. for example, for 20mv output ripple, poscap 2r5tpd680m6 with 6m w are chosen. eripple ripple esri n v d = d . ..(5) number of capacitor is calculated as w = 6m4.6a n 20mv n =1.38 the number of capacitor has to be round up to a integer. choose n =2.
nx2601 14 rev. 2.3 12/01/06 if ceramic capacitors are chosen as output ca- pacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specifi- cation, which results in parallel configuration of multiple capacitors. based on transient requirement typically, the output voltage droop during transient is specified as d v droop d v tran < @step load d i step during the transient, the voltage droop during the transient is composed of two sections. one section is dependent on the esr of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. for example, for the overshoot when load from high load to light load with a d i step tran- sient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation. 2 out overshootstep out v vesri 2lc d=d+t ...(6) where t is the a function of capacitor, etc. crit step outcrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(7) where outouteeout crit stepstep esrcvesrcv l ii == dd ...(8) where esr e and c e represents esr and capaci- tance of each capacitor if multiple capacitors are used in parallel. the above equation shows that if the selected out- put inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the esr of output capacitor. for low frequency capacitor such as electrolytic capacitor, the product of esr and ca- pacitance is high and crit ll is true. in that case, the transient spec is likely to dependent on the esr of ca- pacitor. for most cases, the output capacitors are mul- tiple capacitor in parallel. the number of capacitors can be calculated by the following estep 2 out tranetran esri v n v2lcv d =+t dd ...(9) where crit step eecrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(10) for example, assume voltage droop during tran- sient is 100mv for 15a load step. if the poscap 2r5tpd680m6 (680uf, 6mohm esr) is used, the crticial inductance is given as eeout crit step esrcv l i 6m680f1.2v 0.33h 15a == d wm =m the selected inductor is 0.78uh which is bigger than critical inductance. in that case, the output voltage transient not only dependent on the esr, but also ca- pacitance. number of capacitors is step ee out li esrc v 0.78h15a 6m680f5.67us 1.2v d t=- m =-wm= estep 2 out tranetran 2 esri v n v2lcv 6m15a 100mv 1.2v (5.67us) 20.78h680f100mv 1.3 d =+t dd w =+ mm = the number of capacitors has to satisfied both ripple and transient requirement. overall, we can choose n=2. it should be considered that the proposed equa- tion is based on ideal case, in reality, the droop or over- shoot is typically more than the calculation. the equa- tion gives a good start. for more margin, more capaci- tors have to choose after the test. typically, for high
nx2601 15 rev. 2.3 12/01/06 frequency capacitor such as high quality poscap es- pecially ceramic capacitor, 20% up 100% (for ceramic) more capacitors have to be chosen since the esr of capacitors is so low that the pcb parasitics can affect the results tremendously. more capacitors have to be selected to compensate these parasitic parameters. compensator design due to the double pole generated by lc filter of the power stage, the power system has 180 o phase shift , and therefore, is unstable by itself. in order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin.ideally,the bode plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency, phase margin greater than 50 o and the gain crossing 0db with - 20db/decade. power stage output capacitors usually decide the compensator type. if electrolytic capacitors are chosen as output capacitors, type ii compensator can be used to compensate the system, because the zero caused by output capacitor esr is lower than cross- over frequency. otherwise type iii compensator should be chosen. a. type iii compensator design for low esr output capacitors, typically such as sanyo oscon and poscap, the frequency of esr zero caused by output capacitors is higher than the cross- over frequency. in this case, it is necessary to compen- sate the system with type iii compensator. the follow- ing figures and equations show how to realize the type iii compensator by voltage mode amplifier. z1 42 z2 233 p1 33 p2 12 4 12 1 f ...(11) 2rc 1 f ...(12) 2(rr)c 1 f ...(13) 2rc 1 f ...(14) cc 2r cc = p = p+ = p = p + where f z1 ,f z2 ,f p1 and f p2 are poles and zeros in the compensator. their locations are shown in figure 15. the transfer function of type iii compensator is given by: [ ] ( ) 42233 e 21 out 221 433 21 (1src)1s(rr)c v 1 cc vsr(cc) (1sr)1src cc +++ = + ++ + zin zf vout vref fb r2 r1 r3 r4 c3 c1 c2 ve 40db/decade 20db/decade gain(db) loop gain lc f esr f compensator power stage f z1 z2 f o f f p2 p1 f figure 15 - type iii compensator and its bode plot
nx2601 16 rev. 2.3 12/01/06 t he crossover frequency usually is selected as f lc nx2601 17 rev. 2.3 12/01/06 r3 c1 c2 ve vout vref fb r2 r1 gain(db) compensator loop gain power stage 40db/decade 20db/decade gain f z lc f esr f o f f p figure 16 - type ii compensator and its bode plot for type ii compensator, f o has to satisfy f lc >f esr . 3. set r 2 equal to10k w . based on output voltage, using equation 18, the final selection of r 1 is 20k w. 4.calculate r 3 value by the following equation. osco 32 in v2fl r=r vesr 1v220khz1.5uh =10k 12v6.33m =24.8k p p w w w choose r 3 =24.8k w. 5. calculate c 1 by setting compensator zero f z at 75% of the lc double pole. 1 3z 1 c= 2rf 1 = 224.8k0.751.94khz =4.4nf p pw choose c 1 =4.7nf. 6. calculate c 2 by setting compensator pole p f at half the swithing frequency. 2 3s 1 c= rf 1 = 24.8k200khz =64pf p pw choose c 2 =68pf
nx2601 18 rev. 2.3 12/01/06 output voltage calculation output voltage is set by reference voltage and external voltage divider. the reference voltage is fixed at 0.8v. the divider consists of two ratioed resistors so that the output voltage applied at the fb pin is 0.8v when the output voltage is at the desired value. the following equation and picture show the relationship between out v , ref v and voltage divider. . 2ref 1 out ref rv r= v-v ...(18) where r 2 is part of the compensator, and the value of r 1 value can be set by voltage divider. choose r 2 =10k w , to set the output voltage at 1.8v, the result of r 1 is 8k w . vout vref fb r2 r1 voltage divider figure 17 - voltage divider in general, the minimum output load impedance including the resistor divider should be less than 5k w to prevent overcharge the output voltage by leakage cur- rent (e.g. error amplifier feedback pin bias current). a minimum load for 5k w less (<1/16w for most of applica- tion) is recommended to put at the output. for example, in this application, vout=1.6v the power loss is 1/16w less load r1.6v1.6v/(1/16w)40 ==w select minimum load is 1k w should be good enough. input capacitor selection input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. ceramic ca- pacitors bypass the high frequency noise, and bulk ca- pacitors supply current to the mosfets. usually 1uf ceramic capacitor is chosen to decouple the high fre- quency noise. the bulk input capacitors are decided by voltage rating and rms current rating. the rms current in the input capacitor can be calculated rmsout out in iid1-d v d v = = ...(19) v in = 12v, v out =1.2v, i out =15a, using equation (19), the result of input rms current is 4.5a. for higher efficiency, low esr capacitors are recommended. two sanyo os-con svpa180m 16v 180uf 29m o with 3.4a rms rating are chosen as input bulk capacitors. power mosfets selection the nx2601 requires two n-channel power mosfets. the selection of mosfets is based on maximum drain source voltage, gate source voltage, maximum current rating, mosfet on resistance and power dissipation. the main consideration is the power loss contribution of mosfets to the overall converter efficiency. in this design example, two irfr3706 are used. they have the following parameters: v ds =30v, i d =75a,r dson =9m w ,q gate =23nc. there are three factors causing the mosfet power loss:conduction loss, switching loss and gate driver loss. gate driver loss is the loss generated by discharg- ing the gate capacitor and is dissipated in driver circuits. it is proportional to frequency and is defined as: gatehgatehgslgatelgss p(qvqv)f =+ ...(20) where q hgate is the high side mosfets gate charge,q lgate is the low side mosfets gate charge,v hgs is the high side gate source voltage, and v lgs is the low side gate source voltage. according to equation (3), p gate =0.07w. this power dissipation should not exceed maximum power dissipation of the driver device. conduction loss is simply defined as:
nx2601 19 rev. 2.3 12/01/06 2 hconoutds(on) 2 lconoutds(on) totalhconlcon p=idrk p=i(1d)rk p=pp - + ...(21) where the r ds(on) will increases as mosfet junc- tion temperature increases, k is r ds(on) temperature dependency. as a result, r ds(on) should be selected for the worst case, in which k equals to 1.4 at 125 o c according to irfr3706 datasheet. using equation (4), the result of p total is 0.54w. conduction loss should not exceed package rating or overall system thermal budget. switching loss is mainly caused by crossover con- duction at the switching transition. the total switching loss can be approximated. swinoutsws 1 pvitf 2 = . ..(22) where i out is output current, t sw is the sum of t r and t f which can be found in mosfet datasheet, and f s is switching frequency. the result of p sw is 1.5w. swithing loss p sw is frequency dependent. soft start and enable nx2601 has two switching controller and one ldo controller. each of them has individual digital soft start. each channel has one enable pin for start up. when the power ready (por) signal is high and the voltage at enable pin is above 1.25v, the internal digital counter starts to operate and the voltage at positive input of error amplifier starts to increase, the feedback network will force the output voltage follows the reference and starts the output slowly. after 2048 cycles, the soft start is complete and the output voltage is regulated to the de- sired voltage decided by the feedback resistor divider por digital start up 1.25/1.15 + vbus r1 r2 ensw1 10k on off figure 18 - enable and shut down the nx2601 with enable pin. the start up of nx2601 can be programmed through resistor divider at enable pin. for example, for channel 1, if the input bus voltage is 12v and we want nx2601 starts when vbus is above 8v. we can select r2=1.24k 2 1 (8v1.25v)r r6.8k 1.25v - ==w the nx2601 can be turned off by pulling down the enable pin by extra signal mosfet as shown in the above figure. when enable pin (ensw1) is below 1.15v, the digital soft start is reset to zero. in addition, all the high side is off and output voltage is turned off. frequency selection the frequency can be set by external rt resistor. the relationship between frequency and rt pin is shown as follows. frequency(khz) vs. rt 0 100 200 300 400 500 600 700 800 900 20 30 40 50 60 70 rt(kohm) frequency(khz) figure 19 - frequency versus rt resistor for example, for 300khz operation, rt is about 62kohm. over current limit protection over current limit for step down converter is achieved by sensing current through the low side
nx2601 20 rev. 2.3 12/01/06 mosfet. inside nx2601, the current through rt pin is mirrored and injecting to the pin ocp. since the current through rt pin is decided as rt t 1.25 i= r this current is very accurate and does not change with silicon process and temperature, the over current limit tripping point can be set more accurate than tradi- tional current source. this scheme is the property of nexsem. when synchronous fet is on, the voltage at node sw is given as swldson v=-ir the voltage at pin ocp is given as ocpocpsw ir+v when the voltage is below zero, the over current occurs. the over current limit can be set by the following equation setrtocpdson iir/r = for example, for 20a current limit and 9mohm rdson for irfr3706, the ocp set resistor is calculated as rt 1.25v i20ua 62k == set ocpdson rt i 20a rr9mohm9kohm i20ua === select ocp set resistor r=10.5k. for nx2601, if one channel goes to hiccup current limit, the other channels include ldo will go to hiccup too. ldo selection guide nx2601 offers a ldo controller. the selection of mosfet to meet ldo is more straight forward. the selection is that the rdson of mosfet should meet the dropout requirement. for example. v ldoin =3.3v v ldoout =2.5v i load =2a the maximum rdson of mosfet should be rdsonldoinldooutload r(vv)i (3.3v2.5v)/2a0.4 =- =-=w most of mosfets can meet the requirement. more important is that mosfet has to be selected right pack- age to handle the thermal capability. for ldo, maxi- mum power dissipation is given as lossldoinldooutload p(vv)i (3.3v2.5v)2a1.6w =- =-= select ir mosfet irfr3706 with 9m w r dson is sufficient. ldo compensation the diagram of ldo controller including vcc regu- lator is shown in above figure 20. for low frequency capacitor such as electrolytic, poscap, oscon, etc, the compensation parameter can be calculated as fol- lows. m c of1m gesr 1 c= 2fr1+gesr p where f o is the desired loop gain. r r rc cc + ldo input rload esr co vref f1 f2 figure 20 - nx2601 ldo controller. typically, f o has to be higher than zero caused by esr. f o is typically around several tens khz to a few hundred khz. for this example, we select fo=100khz. g m is the forward trans-conductance of mosfet. for irfr3706, g m =53. select r f1 =5kohm. output capacitor is sanyo poscap 4tpe150mi with 150uf, esr=18mohm. c 15318m c= =155pf 2100khz5k1+5318m w pww choose c c =150pf.
nx2601 21 rev. 2.3 12/01/06 for electrolytic or poscap, r c is typically selected to be zero. r f2 is determined by the desired output voltage f2f1refldooutref rrv/(vv) 5k0.8v/(2.5v0.8)2.35k =- =w-=w choose r f2 =2.34k w. current limit for ldo current limit of ldo is achieved by sensing the ldo feedback voltage. when ldo_fb pin is below 0.4v, the ic goes into hiccup mode. the ic will turn off all the channel (channel 1 and channel 2 ) for 2096 cycles and start to restart system again. layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. there are two sets of components considered in the layout which are power components and small sig- nal components. power components usually consist of input capacitors, high-side mosfet, low-side mosfet, inductor and output capacitors. a noisy environment is generated by the power components due to the switch- ing power. small signal components are connected to sensitive pins or nodes. a multilayer layout which in- cludes power plane, ground plane and signal plane is recommended . layout guidelines: 1. first put all the power components in the top layer connected by wide, copper filled areas. the input capacitor, inductor, output capacitor and the mosfets should be close to each other as possible. this helps to reduce the emi radiated by the power loop due to the high switching currents through them. 2. low esr capacitor which can handle input rms ripple current and a high frequency decoupling ceramic cap which usually is 1uf need to be practically touch- ing the drain pin of the upper mosfet, a plane connec- tion is a must. 3. the output capacitors should be placed as close as to the load as possible and plane connection is re- quired. 4. drain of the low-side mosfet and source of the high-side mosfet need to be connected thru a plane ans as close as possible. a snubber nedds to be placed as close to this junction as possible. 5. source of the lower mosfet needs to be con- nected to the gnd plane with multiple vias. one is not enough. this is very important. the same applies to the output capacitors and input capacitors. 6. hdrv and ldrv pins should be as close to mosfet gate as possible. the gate traces should be wide and short. a place for gate drv resistors is needed to fine tune noise if needed. 7. vcc capacitor, bst capacitor or any other by- passing capacitor needs to be placed first around the ic and as close as possible. the capacitor on comp to gnd or comp back to fb needs to be place as close to the pin as well as resistor divider. 8. the output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. all gnds need to go directly thru via to gnd plane. 10. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. 11. in multilayer pcb, separate power ground and analog ground. these two grounds must be connected together on the pc board layout at a single point. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive ana- log control function.
nx2601 22 rev. 2.3 12/01/06 0 4 5 150pf c18 150uf c19 150uf c20 2n3904 47pf c16 68uf c17 31 30 6 2 1 3 7 8 9 10 11 n x 2 6 0 1 +2.5v/2a vout3 +3.3v vin2 +5v r24 100k c21 1nf r22 6.8k 1.25k r23 r20 6.8k 1.25k r21 r18 1.5k 1.25k r19 r16 5k 2.35k r17 r15 m5 1uf c15 10 r12 5k gnd vref vp rt ensw2 ensw1 enldo ldo fb ldo out reg out reg fb vcc 10.5k r1 1uf c1 c5 4.7nf c3 c2 d1 r4 20.8k 28 29 27 +12v vin1 +5v +1.2v@15a vout1 r3 10k 100uf 180uf r5 24.8k l1 1uh 21 23 0.1uf c4 24 3 x (1500uf,19mohm) c7 l2 1.5uh m2 m1 25 26 22 pvcc1 ocp1 pgnd1 bst1 fb1 comp1 sw1 hdrv1 ldrv1 3k r6 1uf c8 c12 4.7nf c9 d2 r9 10k 13 12 14 +1.6v/10a vout2 r8 10k 180uf r10 25k 20 18 0.1uf c11 17 2 x (1500uf,19mohm) c14 l4 1.5uh m4 m3 16 15 19 pvcc2 ocp2 pgnd2 bst2 fb2 comp2 sw2 hdrv2 ldrv2 auxvcc 1.65k r13 r11 +5v c22 68pf c23 68pf vin1 vin1 1uf c24 1uf c25 off on 2n3904 10k r27 r28 10k off on 2n3904 10k r25 r26 10k figure 21 - nx2601 application with electrolytic capacitors as output capacitors typical applications
nx2601 23 rev. 2.3 12/01/06 typical applications(cont') figure 22 - nx2601 application with ceramic capacitors as output capacitors 2.5k 4 5 100pf c18 47uf c19 10uf c20 2n3904 33pf c16 2.2uf c17 31 30 6 2 1 3 7 8 9 10 11 n x 2 6 0 1 +2.5v/2a vout3 +3.3v vin2 r24 30k c21 1nf r22 6.8k 1.25k r23 r20 6.8k 1.25k r21 r18 1.5k 1.25k r19 r16 5k 2.35k r17 r15 m5 1uf c15 10 r12 5k gnd vref vp rt ensw2 ensw1 enldo ldo fb ldo out reg out reg fb vcc 10.5k r1 1uf c1 c5 3.9nf c3 c2 d1 r4 22k 28 29 27 +12v vin1 +5v +1.2v@10a vout1 r3 11k 100uf 180uf r5 5k l1 1uh 21 23 0.1uf c4 24 6 x 47uf c7 l2 0.68uh m2 m1 25 26 22 pvcc1 ocp1 pgnd1 bst1 fb1 comp1 sw1 hdrv1 ldrv1 3k r6 1uf c8 c12 3.9nf c9 d2 r9 8.9k 13 12 14 +1.8v/5a vout2 r8 11k 39uf r10 5k 20 18 0.1uf c11 17 2 x47uf c14 l4 2.2uh m4 m3 16 15 19 pvcc2 ocp2 pgnd2 bst2 fb2 comp2 sw2 hdrv2 ldrv2 auxvcc 1.65k r13 r11 +5v c22 100pf c23 100pf vin1 vin1 1uf c24 1uf c25 off on 2n3904 10k r27 r28 10k off on 2n3904 10k r25 r26 10k c6 r2 1.2nf 440 c6 r7 1.2nf 440 10k r29 +5v
nx2601 24 rev. 2.3 12/01/06 mlpq 32 pin 5 x 5 package outline dimensions 32 pin 5 x 5 symbol name min nom max a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20ref b 0.18 0.2 5 0.30 d 5.00bsc d2 3.30 3.45 3.55 e 5.00bsc e2 3.30 3.45 3.55 e 0.50bsc l 0.30 0.40 0.50 r 0.09 --- --- nd 6 ne 6 note: all dimensions are displayed in millimeters. nd and ne refer to the number of terminals on each d and e side respectively. a3 a1 side view plane a seating d d/2 e top view e/2 exposed pad l b d2/2 d2 e2/2 2 1 e2 n n-1 btm view r e
nx2601 25 rev. 2.3 12/01/06 mlpq 32 pin 5 x 5 tape and reel information note: 1. r7 = 7 inch lock reel, r13 = 13 inch lock reel. 2. all dimensions are displayed in millimeters.

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